Problem 3: Consider the following MIPS processor:
Instruction [15:11]
Read
Register 1
Instruction [25:21]
Read
Register 2
0
Write
Register
Instruction [20:16]
Read
Data 1
Read
Data 2
1
If $s1 = 0xE0E87920 and $s2 = 0x60EBA860, what will be written in the òite Register©f the following instruction is executed using the above data path?
sub
$t0, $s1, $s2
Problem 4: Assume the following latencies in MIPS pipeline:
IF
250 ps
ID
120 ps
EXE
275 ps
MEM
275 ps
WB
150 ps
The following code is run on this MIPS architecture.
L1:
addi $s0, Szero, 400
lw
$s1, 0($s1)
lw
$s2, 12($s2)
add $s3, $s1, $s2
sw
$s3, 0($s2)
addi $s0, $s0, -1
bnez $s1, L1
Resolve all hazards and calculate the time that it takes for the above code to run in non-pipelined as
well as in pipelined manner. Assume that the result of branch instruction (new PC content) is
available after the EXE stage.
2
Problem 5: Highlight the data path that is active during the execution of the following MIPS
instruction.
1.
2.
3.
4.
Write the register IDs that are read from or written to in the data path,
Show the (number) inputs to the ALU;
Give the value of ALU operation;
Explicitly write the values of all control signals.
lw $t0, 0x8F32($s1)
Problem 6: Consider the following series of instructions:
add
xor
lw
sub
$t0, $s0, $s1
$t1, $t0, $s2
$s0, -12($a0)
$s5, $s0, $s1
a) Identify all the data hazards in the following sequence of instructions. For each hazard, state
the register involved, the writing instruction (by number) and the reading instruction (by
number).
b) Is it possible to resolve any of the hazards you identified in the previous part by reordering the
instructions so that forwarding would be unnecessary? If yes, show how. If not, explain why
not.
3

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