CSCE 5610 University of Texas Computer System Architecture Computer Science Task
Description
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SimpleScalar Assignment
Due April 14, 2022
Introduction
This assignment will require you to use the SimpleScalar tool to measure executions times on a
few benchmarks while you change various SimpleScalar parameters. It is intended to help you
understand what is involved in analyzing the architecture in simulated programs.
Parameters to adjust:
Cache configuration takes the following format
::::
cache name, must be unique.
number of sets in the cache.
block size
associativity of the cache
replacement policy (l | f | r), where l = LRU, f = FIFO, r = random replacement
For this assignment use the following L1 Instruction and L1 Data cache and NO L2 cache.
-cache:il1 il1:128:32:1:l -cache:il2 none -cache:dl1 dl1:128:32:1:l -cache:dl2 none -cache:dl1lat 1
-cache:il1lat 1 -mem:lat 18 2
The cache latency (both instruction and data) is specified as 1 cycle. The memory configuration
indicates that the memory has a latency of 18 cycles (to get the first byte of the memory) and the
entire memory word (default is 8 bytes) takes 2 additional cycles
Since the purpose of using Simplescalar is to study pipeline design and branch predictions, we will
use only one cache configuration. However, we will investigate several different pipeline design
parameters and branch prediction techniques
You will be required to change the following parameters with the appropriate flag:
(Note: these parameters are defined in more detail below)
et the Instruction Fetch Width ¥tch:ifqsize
pdate size of RUU model µu:size
pdate size of the load/store queue -lsq:size
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