CSE/EEE 230 Fall 2022
Extra Assignment
Show the complete work, including intermediate steps to receive full credit for any question.
C Code: (For questions 1-4)
int main(){
int* array = 0x1ABCD004, int n = 8;
function(array, n);
}
void function(int array[], int n){
for(int i = n; i > n/2; i–)
array[i] = array[i-n/2] + array[0];
}
Question 1: (10 points)
Write the MIPS code for the given C code. You may use pseudo instructions. Assume that base address
of array is in register $s0 and the size of the array, n is stored in the register $s1.
Question 2: (10 points)
Write the machine code (in hexadecimal), assuming that the PC corresponding the start of the program
(main) is 0x40800.
Question 3: (10 points)
Write the complete 5-stage pipeline implementation assuming the architecture has forwarding unit,
hazard detection unit and no structural hazards. Also, assume that MIPS uses 2-bit branch prediction
and the current state is weak Branch Not Taken state.
Question 4: (10 points)
Show the implementation of (a) a direct mapped instruction cache with four 4-word blocks and (b) a 2way set associative data cache with four 2-word blocks for the given code. Show the cache whenever a
block is added or replaced.
Question 5: Virtual Memory (10 points)
Assume that both virtual and physical addresses are 32-bits and the size of a page is 4K Bytes.
Table 5.1 shows some of the entries in a Page Table and Table 5.2 shows a 2-way cache of 4 sets and 2word blocks. Assume that the data in the cache is such that the least significant byte corresponds to the
lowest address in the block.
Write the TLB entries when an application accesses the following virtual addresses. Also, write the
words (data or memory contents) corresponding to these addresses.
(a) 0x026DE008
(b) 0x00480484
(c) 0x10000ABC
Index
Valid bit
Dirty bit

Physical Page number
0x0
0
0
0x17654
0x52
1
1
0x12480
0x480
1
0
0x13208
0xABC
0
0
0x12345
0x1234
1
1
0x18765
0x26DE
1
1
0x148C0
0x10000
1
0
0x19000
0xFFFFF
0
0
0x11111
(d) 0x00052260
Table 5.1 age Table (some entries)
Table 5.2 2-way set associative Data Cache
1
0x124802 (011)2
0x81623800045600
1
0x132084 (100)2
0x8013650808040608
1
0x187654 (010)2
0x16BC6791010DE0
1
0x148C0E (000)2
0x0016023810148A00
1
0x132084 (100)2
0x04560890A06B458
1
0x19000A (101)2
0xDEF00012345600
1
0x19000B (100)2
0x6540032100ABC

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